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<div class="header">
  <div class="headertitle"><div class="title">I2S (Inter-IC Sound)<div class="ingroups"><a class="el" href="group__group__hal__impl.html">CAT1 Implementation Specific</a></div></div></div>
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<p >The CAT1 (PSoC™ 6) I2S Supports the following values for word lengths: </p>
<ul>
<li>8 bits</li>
<li>10 bits (CAT1B only)</li>
<li>12 bits (CAT1B only)</li>
<li>14 bits (CAT1B only)</li>
<li>16 bits</li>
<li>18 bits</li>
<li>20 bits</li>
<li>24 bits</li>
<li>32 bits</li>
</ul>
<p >The channel length must be greater than or equal to the word length. On CAT1A devices, the set of supported channel lengths is the same as the set of supported word lengths. On CAT1B devices, the channel length may be any value between 8 and 32 bits.</p>
<p >The sclk signal is formed by integer division of the input clock source (either internally provided or from the mclk pin). The CAT1A I2S supports sclk divider values from 1 to 64. On CAT1B devices, the I2S supports sclk divider values from 2 to 256.</p>
<p >On CAT1A devices, if both RX and TX are used, the same GPIO must be specified for mclk in both directions. See the device datasheet for more details on valid pin selections.</p>
<p >The following events are not supported on CAT1B:</p><ul>
<li><a class="el" href="group__group__hal__i2s.html#gga98bc78188673aae2c4e27b660a3f20feaf860cfe6a5c38f054a44b53f854c8126">CYHAL_I2S_TX_EMPTY</a></li>
<li><a class="el" href="group__group__hal__i2s.html#gga98bc78188673aae2c4e27b660a3f20feab3afa80998f12db882eea775c8076b33">CYHAL_I2S_TX_NOT_FULL</a></li>
<li><a class="el" href="group__group__hal__i2s.html#gga98bc78188673aae2c4e27b660a3f20feaef9405281e230cb6b518d1649293d3f0">CYHAL_I2S_RX_FULL</a></li>
<li><a class="el" href="group__group__hal__i2s.html#gga98bc78188673aae2c4e27b660a3f20fea5b792c472fda8fe9b0580b48dc3f82cc">CYHAL_I2S_RX_NOT_EMPTY</a></li>
</ul>
<dl class="section note"><dt>Note</dt><dd>If the I2S hardware is initialized with a configurator-generated configuration via the <a class="el" href="group__group__hal__i2s.html#ga061f2ea2ce311e9f36e0a5bde2580cc6">cyhal_i2s_init_cfg</a> function, the <a class="el" href="group__group__hal__i2s.html#gga98bc78188673aae2c4e27b660a3f20feab4ce24b585402763c519a85ffa67cecf">CYHAL_I2S_TX_HALF_EMPTY</a> and <a class="el" href="group__group__hal__i2s.html#gga98bc78188673aae2c4e27b660a3f20feaf6a846640d1ecc585d2047f689992c30">CYHAL_I2S_RX_HALF_FULL</a> events will be raised at the configurator defined TX and RX FIFO trigger levels, respectively, instead of their usual trigger level of half the FIFO depth.</dd></dl>
<h1><a class="anchor" id="section_psoc6_i2s_output_signals_behavior"></a>
MXTDM SCLK/WS output signals behavior</h1>
<p >On devices with MXTDM IP block (e.g. CAT1B devices), in master role, I2S' SCK and WS signals starts toggling upon cyhal_i2s_init function call, while data is being transmitted / received after corresponding cyhal_i2s_start_* functions call. This is different to the behavior of MXAUDIOSS-based I2S (e.g. CAT1A, CAT1C devices), where SCK and WS signals starts toggling along with data receive / transmit process is being started with corresponding cyhal_i2s_start_* function call. This is important for power efficient applications. For them, it is recommended to init i2s master using <a class="el" href="group__group__hal__i2s.html#gad1008bd6dc716300e3e7d5482390eaf1">cyhal_i2s_init</a> right before data transfers are performed and deinit it using <a class="el" href="group__group__hal__i2s.html#gabda3b41391e8567f52599268dd6b721e">cyhal_i2s_free</a> when no i2s transmission is expected in nearest time, to save power. </p>
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